Interface Protocol

The configuration and control of Tibbit #64-1 is conducted via several registers. General registers affect the operation of the Tibbit as a whole, while the channel-specific registers affect only their respective channels.


General Registers

Register Name

Register Address

Size (bytes)

R/W

Description

I2C_ADDR

0x00

1

R/WP

The Tibbit's I²C peripheral address, which is 0xB0 by default. This register is stored in the Tibbit's non-volatile memory and is write-protected.

ID

0x01 (MSB)

0x02 (LSB)

1

R/WP

The Tibbit's ID, which can be changed to any value from its default of 0x641. This register is stored in the Tibbit's non-volatile memory and is write-protected.

LOCK

0x03

1

R/W

Determines whether write-protected registers are locked. When the value of this register is 0x00, write-protected (WP) registers cannot be changed. To enable writing to write-protected registers, change this value to 0xAA.
This register is stored in the Tibbit's RAM. Resetting or power-cycling the module will clear this register, locking all write-protected registers.

FW_VERSION

0x04 (MSB)

0x05 (LSB)

2

R

The Tibbit's firmware version, which begins with 64.

SIGNATURE

0x06 (MSB)

0x07 (LSB)

2

R/W

Used as a signature to check communications. Its value is 0xAA55.

FRQ_RNG

0x08

1

R/W

Determines the frequency range of all channels' output. The available options are:

  • 0 — 1Hz ~ 2,499Hz
  • 1 — 2,500Hz ~ 4,999Hz
  • 2 — 5,000Hz ~ 20kHz

If this register is set to anything other than one of these three values, the range will be set to 5kHz ~ 20kHz.

Note: Setting this register will reset every channel's frequency to their default values and disable all outputs.

RESERVED

0x09

1

R/W

Reserved for future use.

RESERVED

0x0A

1

R/W

Reserved for future use.

R = read-only, R/W = read/write, R/WP = read/write-protected (the LOCK register must be changed to 0xAA to enable writing)


Channel-Specific Registers

Register Name

Register Address

Size (bytes)

R/W

Description

CH1_FRQ

0x0B (MSB)

0x0C (LSB)

2

R/W

The frequency of channel 1. Acceptable values are integers from 1 to 5,000, as well as multiples of 100 from 5,000 to 20,000. Writing a value greater than 20,000 or an integer between 5,000 and 20,000 that is not a multiple of 100 will result in the channel entering the fault status.

The default value is dependent on the frequency range:

  • 1Hz ~ 2,499Hz — 1,000
  • 2,500Hz ~ 4,999Hz — 3,000
  • 5,000Hz ~ 20kHz — 10,000

Setting the value of this register to 0 turns the channel's output off constantly. This is equivalent to a 0% duty cycle and constantly OFF output.

CH1_DUTY_CYCLE

0x0D

1

R/W

The duty cycle of channel 1. The default value is 50. Acceptable values are integers from 0 to 100. Writing 0 to this register turns off the channel's output, even if it has been enabled. Writing a value exceeding 100 will result in the channel's output being disabled and a fault being generated.

CH1_ENABLE

0x0E

1

R/W

Determines whether output for channel 1 is enabled. The default value is 0x00 — the channel is disabled. Writing any value other than 0 enables the channel. Writing 0x00 to to this register overrides any other expected function, such as frequency being set to 0.

CH1_FAULT

0x0F

1

R

The fault register for channel 1. The default value is 0x00 — there is no fault.

If this register reads 0x01, it means that an out-of-bound frequency has been specified for the channel. For example, if the frequency for channel 1 has been set to a value outside of the range specified by FRQ_RNG. This value is also returned if the user specifies a frequency above 5kHz that is not divisible by 100.

If this register reads 0x02, it means that the frequency registers for this channel were written in the wrong order.

If this register reads 0x03, it means that the duty cycle specified for this channel is outside the acceptable range (0% ~ 100%).

When a fault occurs, the Tibbit disables the channel's output and waits for the misconfiguration to be corrected. Once all issues have been resolved, the value of this register returns to 0x00.

CH2_FRQ

0x10 (MSB)

0x11 (LSB)

2

R/W

The frequency of channel2. Acceptable values are integers from 1 to 5,000, as well as multiples of 100 from 5,000 to 20,000. Writing a value greater than 20,000 or an integer between 5,000 and 20,000 that is not a multiple of 100 will result in the channel entering the fault status.

The default value is dependent on the frequency range:

  • 1Hz ~ 2,499Hz — 1,000
  • 2,500Hz ~ 4,999Hz — 3,000
  • 5,000Hz ~ 20kHz — 10,000

Setting the value of this register to 0 turns the channel's output off constantly. This is equivalent to a 0% duty cycle and constantly OFF output.

CH2_DUTY_CYCLE

0x12

1

R/W

The duty cycle of channel 2. The default value is 50. Acceptable values are integers from 0 to 100. Writing 0 to this register turns off the channel's output, even if it has been enabled. Writing a value exceeding 100 will result in the channel's output being disabled and a fault being generated.

CH2_ENABLE

0x13

1

R/W

Determines whether output for channel 2 is enabled. The default value is 0x00 — the channel is disabled. Writing any value other than 0 enables the channel. Writing 0x00 to to this register overrides any other expected function, such as frequency being set to 0.

CH2_FAULT

0x14

1

R

The fault register for channel 2. The default value is 0x00 — there is no fault.

If this register reads 0x01, it means that an out-of-bound frequency has been specified for the channel. For example, if the frequency for channel 2 has been set to a value outside of the range specified by FRQ_RNG. This value is also returned if the user specifies a frequency above 5kHz that is not divisible by 100.

If this register reads 0x02, it means the frequency registers for this channel were written in the wrong order.

If this register reads 0x03, it means that the duty cycle specified for this channel is outside the acceptable range (0% ~ 100%).

When a fault occurs, the Tibbit disables the channel's output and waits for the misconfiguration to be corrected. Once all issues have been resolved, the value of this register returns to 0x00.

CH3_FRQ

0x15 (MSB)

0x16 (LSB)

2

R/W

The frequency of channel 3. Acceptable values are integers from 1 to 5,000, as well as multiples of 100 from 5,000 to 20,000. Writing a value greater than 20,000 or an integer between 5,000 and 20,000 that is not a multiple of 100 will result in the channel entering the fault status.

The default value is dependent on the frequency range:

  • 1Hz ~ 2,499Hz — 1,000
  • 2,500Hz ~ 4,999Hz — 3,000
  • 5,000Hz ~ 20kHz — 10,000

Setting the value of this register to 0 turns the channel's output off constantly. This is equivalent to a 0% duty cycle and constantly OFF output.

CH3_DUTY_CYCLE

0x17

1

R/W

The duty cycle of channel 3. The default value is 50. Acceptable values are integers from 0 to 100. Writing 0 to this register turns off the channel's output, even if it has been enabled. Writing a value exceeding 100 will result in the channel's output being disabled and a fault being generated.

CH3_ENABLE

0x18

1

R/W

Determines whether output for channel 3 is enabled. The default value is 0x00 — the channel is disabled. Writing any value other than 0 enables the channel. Writing 0x00 to to this register overrides any other expected function, such as frequency being set to 0.

CH3_FAULT

0x19

1

R

The fault register for channel 3. The default value is 0x00 — there is no fault.

If this register reads 0x01, it means that an out-of-bound frequency has been specified for the channel. For example, if the frequency for channel 1 has been set to a value outside of the range specified by FRQ_RNG. This value is also returned if the user specifies a frequency above 5kHz that is not divisible by 100.

If this register reads 0x02, it means the frequency registers for this channel were written in the wrong order.

If this register reads 0x03, it means that the duty cycle specified for this channel is outside the acceptable range (0% ~ 100%).

When a fault occurs, the Tibbit disables the channel's output and waits for the misconfiguration to be corrected. Once all issues have been resolved, the value of this register returns to 0x00.

R = read-only, R/W = read-write


Interface Protocol

General Registers

Channel-Specific Registers