PLL Management

The phase-locked loop (PLL) is a module of the device that transforms the clock generated by the onboard crystal into a higher frequency (x8 of the base for Tibbo devices). When the PLL is on, the device runs at eight times the base frequency; when the PLL is off, the device runs at the "native" frequency of the crystal. Naturally, the device is eight times faster (and consumes almost as much more power) when the PLL is on.

Not all Tibbo devices have the PLL — to find out if yours does, refer to its platform documentation (for example, the EM1000's is here).

When a certain platform supports the PLL, it will have a sys.currentpll read-only property and the sys.newpll method to control the PLL. Due to the nature of PLL operation, it is impossible to switch it on and off while the CPU is executing the firmware. The PLL needs time to "stabilize" its output frequency and it is not safe to let this happen when the CPU is running. Instead, the PLL is toggled when the CPU is in the reset state.

To change the PLL mode, request the new state through the sys.newpll method, then self-reset the device through the sys.reboot method. After the reboot, the device emerges from reset with the new PLL state (and the PLL frequency already stabilized).

Here is a code example that makes sure that your device is running with PLL off:

Tibbo BASIC
sub on_sys_init
	if sys.currentpll=YES then
		sys.newpll(OFF)
		sys.reboot
	end if
end sub

External resets — power-up and RST pin reset (use of the reset button) — set the PLL to the default state (typically ON). On some devices, there is a hardware jumper that defines the post-external reset state of the PLL.

A warning note icon.Notice that PLL mode affects other objects — for example, the baudrates of serial ports (this is why there is a ser.div9600 property) and the frequency generated by the beep. object.