Tiles, Sockets, Connectors, Controls

A block diagram illustrating the layout of the LTPP3(G2).

The LTPP3 (G2) features eight "M" and eight "C" sockets.

Sockets (S1) through (S15) form four standard tiles.

There are 32 control lines connecting the "M" sockets to the CPU, four for each socket.

"M" sockets (S1), (S5), (S9), and (S13) have the UART capability.

All "M" sockets have the interrupt capability.

All "M" sockets have SPI/I²C capability.