General-purpose I/O Lines
The WM2000 has ten general-purpose I/O lines (GPIO0 through GPIO9). All lines are 3.3V CMOS. The maximum load for each I/O line is 12mA, with the exception of lines 2 and 4 (see the Special case section below).
The simplified structure of one I/O line of the WM2000 is shown in the circuit diagram below. Each line has an independent output buffer control. When the WM2000 powers up, all its I/O lines are configured as inputs. You need to explicitly enable the output buffer of a specific I/O line if you want it to become an output.
Many of the WM2000's control lines also serve as inputs or outputs of special-function modules, such as serial ports. The majority of these lines need to be correctly configured as inputs or outputs — this won't happen automatically. Several lines — such as the TX and RX lines of the serial ports when in UART mode — are automatically configured as outputs and inputs when the serial port is enabled. For details, see platform-specific information for the WM2000 in the platforms section of the TIDE, TiOS, Tibbo BASIC, and Tibbo C Manual.
When the serial debugging is enabled, the RX and TX lines of UART1 become the RX and TX lines of the debug serial port and cannot be used as GPIO lines or UART1's RX and TX lines.
Each I/O line has a weak pull-up resistor that prevents the line from floating when the output buffer is tri-stated.
GPIO2 and GPIO3 can work as interrupts.
Special case — GPIO lines 1 and 3
GPIO1 and GPIO3 are much weaker than all other GPIOs — the maximum load for each of the two lines is only 500µA. Both lines retain all other functionality. Below is a diagram illustrating the simplified structure of GPIO1 and GPIO3.
In most applications, these two lines will function like any other GPIO. For example, when used for communications (e.g., serial, I²C, SPI), there is absolutely no negative effect stemming from their design difference.
Wiring to other hardware will require additional buffering.
The circuitry of GPIO1 and GPIO3 differs from the rest of the lines because they also act as bootstrap pins of the module's microcontroller. At boot, these lines have to be disconnected from any external circuitry your host board may have to ensure that the WM2000 does not enter the bootloader.
Eight I/O lines are grouped into one primary 8-bit port P0, while the second port — P1 — only has two GPIO lines. P0 and P1 are "pseudo ports," meaning that their GPIO lines actually belong to several different physical ports of the module's microcontroller. As a result, port operations such as io.portset, io.portget, or io.portstate do not access all port pins in perfect unison. In port operations, the writing or reading of some of the port's lines will happen sooner than the writing or reading of other lines. This "dissonance" is very small and will not matter to most applications, but keep in mind that it exists.
I/O line control is described in detail in the documentation for the io. object in the TIDE, TiOS, Tibbo BASIC, and Tibbo C Manual.