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For UART mode (ser.mode= 0- PL_SER_MODE_UART) specifies the time that needs to elapse since the arrival of the most recent serial character into the RX buffer to cause the data to be committed (and on_ser_data_arrival event generated). For Wiegand and clock/data mode (ser.mode= 1- PL_SER_MODE_WIEGAND or 2- PL_SER_MODE_CLOCKDATA) the time since the most recent data bit (high-to-low transition on the W0&1in/cin line) is counted.
In the UART mode this property allows you to combine incoming serial data into larger "chunks", which typically improves performance. Notice, that the intercharacter gap is not counted when the new data is not being received because the serial port has set the RTS line to LOW (not ready). For this to happen, the serial port must be in the UART/full-duplex/flow control mode (ser.mode= 0- PL_SER_MODE_UART, ser.interface= 0- 0- PL_SER_SI_FULLDUPLEX, and ser.flowcontrol= 1- ENABLED) and the RX buffer must be getting nearly full (less than 64 bytes of free space left).
For Wiegand and clock/data modes, counting timeout since the last bit is the only way to determine the end of the data output. Suggested timeout is app. 10 times the bit period of the data output by attached Wiegand or clock/data device.