Enum pl_io_port_num

Top  Previous  Next

Enum pl_io_port_num contains the list of available 8-bit GPIO ports. Use these constants when selecting the port with the io. object (see the io.portnum property).

Note that GPIO lines are of unidirectional type and require explicit configuration as outputs or inputs.

 

On this platform, 8-bit ports are virtual, and some of these ports are "more virtual" than other ports. For compatibility, we've kept the I/O line grouping exactly the same as on the EM1000 platform. The difference is that on the EM1000 8-bit ports are real 8-bit registers that allow clean reading and writing. On the EM2000, the hardware ports are 32-bit registers to begin with. Further, on some ports it wasn't possible to even group the lines together in a manner that would follow the EM1000 port grouping.    

 

Enum pl_io_port_num includes the following constants:

0- PL_IO_PORT_NUM_0:8-bit port 0 (P0). Contains I/O lines 0-7. This is a virtual port. During reads (io.portget, io.portstate(g)) and writes (io.portset, io.portstate(s)) each one of the port's 8 lines is handled individually, starting with line 0 and ending with line 7. Hence, there is a small rolling delay in the state writing and reading.
1- PL_IO_PORT_NUM_1:8-bit port 1 (P1). Contains I/O lines 8-15. This is a virtual port. During reads (io.portget, io.portstate(g)) and writes (io.portset, io.portstate(s)) each one of the port's 8 lines is handled individually, starting with line 0 and ending with line 7. Hence, there is a small rolling delay in the state writing and reading.
2- PL_IO_PORT_NUM_2:8-bit port 2 (P2). Contains I/O lines 16-23. This is a virtual port. During writes (io.portset, io.portstate(s)), all lines with their new value equal to LOW are cleared first, and then the lines with their new value equal to HIGH are set next. Hence, writing is a two-step process that introduces a small delay in LOW->HIGH transitions on the port's lines. Port reads (io.portget, io.portstate(g)) are performed cleanly, in a single step.  
3- PL_IO_PORT_NUM_3:8-bit port 3 (P3). Contains I/O lines 24-31. This is a virtual port. During writes (io.portset, io.portstate(s)), all lines with their new value equal to LOW are cleared first, and then the lines with their new value equal to HIGH are set next. Hence, writing is a two-step process that introduces a small delay in LOW->HIGH transitions on the port's lines. Port reads (io.portget, io.portstate(g)) are performed cleanly, in a single step.
4- PL_IO_PORT_NUM_4:8-bit port 4 (P4). Contains I/O lines 32-39. This is a virtual port. This is a virtual port. During writes (io.portset, io.portstate(s)), all lines with their new value equal to LOW are cleared first, and then the lines with their new value equal to HIGH are set next. Hence, writing is a two-step process that introduces a small delay in LOW->HIGH transitions on the port's lines. Port reads (io.portget, io.portstate(g)) are performed cleanly, in a single step.