Clock Frequency Control
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Some devices support clock frequency (PLL) control. When the PLL is on, the system is running at the highest possible frequency. When the PLL is off, the system is running at a reduced frequency. For example, the EM1000 can run at 88.4736MHz (PLL on) or 11.0592MHz (PLL off).
To find out if your device allows frequency control and what particular frequencies it can operate on, refer to this device's platform documentation (for example, EM1000's is here).
The clock frequency affects all aspects of device operation that rely on this clock. Naturally, program execution speed, too, depends on the clock frequency. Serial port baudrates (see ser.baudrate) in the UART mode (ser.mode= 0- PL_SER_MODE_UART) also depend on the main clock. Finally, the frequency of the square wave generated by the beep. object depends on the main clock as well. The period of the on_sys_timer event of the sys. is not affected by the PLL mode.
After the external reset (see sys.resettype), devices with PLL control may boot with the PLL on or off. Refer to the "Platform-dependent Programming Information" topic inside your device's platform specifications section for more information.