#57, M1S: FPGA Tibbit
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Function: Contains an ICE5LP1K-SWG36ITR50 FPGA from Lattice Semiconductor
Form factor: M1S
Category: Input/output module
Special needs: ---
Power requirements: 5V/25mA
See also: ---
The FPGA Tibbit carries a ICE5LP1K-SWG36ITR50 FPGA from Lattice Semiconductor. The Tibbit is suitable for implementing a wide variety of configurations (functions). The list of currently available configurations is found in Implemented Configurations. Four IO lines of the FPGA are exposed to the outside world. Since the FPGA only works with 3.3V logical signals, there are automatic bi-directional level shifters between the FPGA and pins 2-5 of the Tibbit. "Automatic" means that these level shifters do not require direction control and choose the direction for each IO line automatically, depending on which side (FPGA or an external circuit) is driving this line.
The Tibbit is controlled through a standard SPI interface lines -CS, SCLK, MOSI, and MISO. There are two non-standard features built on top of the SPI interface:
•-CS and SCLK lines are used to produce a reset pulse for the FPGA IC.
•MISO line also doubles as a status (DONE) line.
Both non-standard features are described in Resetting and Initializing the Onboard FPGA.
There are three red LEDs and one green LED. These four LEDs are connected to four interface lines of the Tibbit. LEDs light up for the LOW state of the interface lines.
Red LEDs are connected to the -CS, SCLK, and MOSI lines. The green LED is connected to the DONE/MISO line.
The use of this Tibbit is illustrated by a Tibbo BASIC test project. Yo can find it here: https://github.com/tibbotech/CA-Test-Tibbit-57.