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The D/A converter is based on the Analog Devices' 14-bit AD7836 chip and has 4 independent output channels with 14-bit resulution. Each of the four channels have independent voltage and current output lines (both can be used at the same time if needed).
Each channel has two outputs: one voltage and one current output. The voltage outputs have +/-10V range (20mA max load). Writing all 1's (14 of them) into the D/A channel produces the maximum positive level on the voltage output (+10V nominal), writing all 0's produces the maximum negative level on the voltage output (-10V nominal). Writing a "middle" binary value of "10000000000000" (that's 1 followed by 13 zeroes) produces a 0V output. Of course, this explanation is idealized as it doesn't take into account inevitable conversion errors.
The output current range on the current output is 0-20mA. An external 4-15V power source is required for current outputs to work. Writing all 1's into the D/A channel results the maximum output current. Writing a middle value (10000000000000B) results in zero current. Writing any value below that still produces zero current. Hence, the actual resolution of the current output is not 14, but 13 bits.
The D/A converter has full galvanic isolation from the rest of the IB1004 + SB1004 circuitry: the power for the D/A section is generated by an isolated switching power supply, all control lines use opto-couplers.
All D/A-related lines are available on a 9-pin terminal block #3:
*GPIO line configured as input (default state)
The D/A converter control cycle consists of the following steps. First, a 16-bit data word is serially clocked into the D/A circuit. Bits 15 and 14 of the data word select the output channel, remaining 14 bits carry desired output value. The word is sent most significant bit first.
Two lines -- CLOCK and DATA -- are used for sending the data word to the D/A converter. Inactive state for the CLOCK line is LOW. Each write transaction consists of 16 clock pulses. With each LOW-to-HIGH transition on the CLOCK line, the state of the DATA line is latched into the D/A converter. The process is illustrated below.
Once all 16 bits have been clocked in, the negative pulse on the WR line sets new data and the new analog value appears on the outputs of the corresponding D/A channel (provided that the EN lines is at low).
The EN line is used for enabling the analog outputs of the D/A converter. The system powers up with EN line pulled HIGH internally. This disables the D/A converter and produces 0V (0mA) on its outputs. Taking the EN line LOW will enable the D/A. Before that, your application should write the desired value into each D/A channel. Failure to do so will result in the unknown voltage (current) output levels once the EN line is set LOW.
Remember that you need to configured all four control lines of the EM1000 as outputs.
Clock speed limitations
The D/A converter is electrically isolated from the rest of the device, so there are opto-couplers on all interface lines. Opto-couplers are relatively slow devices. This imposes a limit on how fast the clock line can be toggled. The minimum clock period is 200us. Both half-periods must be at least 100uS long. The minimum pulse width on the WR line is also 100uS. This means that the new value can be output to the converter in 200uS*16+100=3.3ms.