Wiegand and Clock/Data Circuit Examples

Top  Previous  Next

In the Wiegand mode, the W0&1in input of the serial port must receive a logical AND of W0 and W1 output of attached Wiegand device. A simple AND gate will do the job (figure A below). NOR-AND gates are more popular that AND gates, and these can be used too (figure B). In case you are building a product that will also accept clock/data input, you may need to control whether the W0&1in input should receive a logical AND of the two lines, or just one of the lines. Schematic diagram C uses an additional I/O line of the device to control this. When the control line is HIGH the W0&1in input receives a logical AND of both W0 and W1 lines, when the control line is LOW, the W0&1in input receives just the signal from the W0 line. Four gates are required for this, so you will get away with using a single 74HC00 IC.