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The EM2001 has four serial ports that can work in one of the three modes: UART, Wiegand, or clock/data.
UART mode supports full- and half-duplex communications.
Full-duplex interface is typically used for RS232, RS422, full-duplex RS485, or "serial TTL" (CMOS) communications.
In the UART full-duplex mode, each port has TX and RX lines, as well as RTS and CTS lines, which are optionally used for the hardware flow control. When the flow control is enabled, the EM2001 will control the RTS and CTS lines automatically.
Half-duplex interface is typically associated with half-duplex RS485 communications. In this mode, the serial port uses TX, RX, and RTS lines, the latter serving as the direction control line. Direction control is automatic and does not require any intervention from your Tibbo BASIC/C program.
TX and RX lines cannot be relocated. RTS and CTS lines can be moved around. For RTS, any unused GPIO line can be assigned to work as the RTS line of a serial port. For CTS, only interrupt lines I0-7 (GPIO lines 16-23) can be selected. Flexible remapping of RTS and CTS line is facilitated by I/O mapping properties offered by the serial (ser.) object.
DTR and DSR lines often found on RS232 ports are not controlled by the ser. object. It is the responsibility of your Tibbo BASIC/C application to take care of these lines. Therefore, you can choose what GPIO lines of the EM2000 will be used as DTR and DSR lines in your system.
Flexible mapping notwithstanding, Tibbo has defined the default mapping for RTS, CTS, DTR, and DSR lines. This was done in an effort to standardize schematic diagrams across our entire product range. The EM2001 diagram shows such default assignments in BLUE color.
UARTs of the EM2001 module have one significant limitation: it is not possible to simultaneously use the 7 bits/character mode and "no parity" mode. All other modes are supported.
The Wiegand interface is often used in security products. A large number of magnetic card and RFID readers support this interface. The ser. object allows you to both receive and send data streams in the Wiegand format.
"Wiegand" requires only two interface lines -- W0 and W1. Here is how these lines map to the "traditional" lines of the serial port:
As shown in the table, the CTS line is supposed to receive a "logical AND" of incoming W0 and W1 signals. This requires external circuitry -- see Wiegand and Clock/Data Circuit Examples for details. No additional circuitry is required to output Wiegand data.
"W1 output" (on TX) and "W1 input" (on RX) cannot be remapped, while "W0 output" (on RTS) can be reassigned to any suitable GPIO line. "W0 & W1 input" (on CTS) can be remapped, but possible choices are limited to interrupt lines I0-7 (GPIO16-23).
The clock/data interface is also a very popular reader interface. The ser. object allows you to receive and send data streams in the clock/data format.
As the name implies, this interface requires two data lines - CLOCK and DATA. Here is how these lines map to the "traditional" lines of the serial port:
As in the UART mode, "DATA output" (on TX) and "DATA input" (on RX) cannot be remapped, while "CLOCK output" (on RTS) can be reassigned to any suitable GPIO line. "CLOCK input" (on CTS) can be remapped, but possible choices are limited to interrupt lines I0-7 (GPIO16-23).
No additional circuitry is required to handle clock/data streams.
For more information see the documentation for the serial (ser.) object found inside the "TIDE and Tibbo BASIC Manual".